[extropy-chat] diffraction limit

[Dan Clemmensen]

Eugen Leitl wrote:

>On Mon, May 31, 2004 at 08:07:52AM +0200, scerir wrote:
>  
>
>>From: "Dan Clemmensen" 
>>
>>    
>>
>>>>http://www.intel.com/research/documents/Bourianoff-Proc-IEEE-Limits.pdf
>>>>        
>>>>
>>>Thanks! Very interesting paper.
>>>      
>>>
>>There is a comment, on it, here 
>>http://zdnet.com.com/2100-1103_2-5112061.html
>>by Paolo Gargini (Intel Co.)
>>(I had no time to read it though).
>>    
>>
>
>Given that we have working spintronics and molecular transistors the article
>says that certain (accustomed) ways of things won't work. Well, duh. Many
>people tried to prematurely bury Moore, so far unsuccessfully.
>
>Moore's law will tank eventually, but I'm putting that limit at about mole amount
>of switches (not transistors) -- a litre of circuitry, or so.
>
>  
>
The paper we are discussing examines density limits imposed by the 
Heisenberg uncertainty principle on classical electronics, and is 
independent of materials. These limits therefore will apply to molecular 
transistors and all other nano-electronics.  I think they also apply to 
spintronics. They do not apply to nanomechanical computing.

The paper is not about the limits of CMOS, except to note that we may 
not need to abandon CMOS to reach the fundamental Heisenberg limits in 2D.

After thinking about all this, I think we can continue to use 
nanoelectronics for a long time to come by exploiting the third 
dimension. The paper implicitly dismisses this approach because of power 
dissipation. However, there is a mistaken assumption here. When you 
increase the density, you must increase the power to insure that the 
classical signal overcomes the tunneling effects. But what if we use 
nanoelectronics to build highly efficient elements, but keep the 
elements "far apart" in two dimensions. If we keep the element distances 
at 45nm even if the elements themselves are smaller, then tunneling 
effects are not too bad, and we can achieve very good power efficiency. 
That two-dimensional density is still four times today's density. But 
since the system is now very low power, we can stack layers, and 
45nm/layer, and still avoid inter-layer tunneling effects. This allows 
continual doubling until the power dissipation is too high, while still 
staying in the classical electronic regime.

Note that nanoelectronics is likely to be unrelated to photolithography. 
I really hope it can be implemented without the enormous capital costs 
associated with today's silicon Fabs.