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</o:shapelayout></xml><![endif]--></head><body lang=EN-US link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><div style='border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in 0in'><p class=MsoNormal><b>From:</b> extropy-chat <extropy-chat-bounces@lists.extropy.org> <b>On Behalf Of </b>Adrian Tymes via extropy-chat<br><b>Subject:</b> Re: [ExI] World's Largest Chip<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p></div><p class=MsoNormal><span style='font-size:13.5pt'>A company called</span><span class=gmaildefault><span style='font-size:13.5pt;font-family:"Arial",sans-serif'> "</span></span><span style='font-size:13.5pt'>Cerebra</span><span class=gmaildefault><span style='font-size:13.5pt;font-family:"Arial",sans-serif'>" has made the world's largest Microprocessor chip, it contains 850,000 cores and 2.6 <b>Trillion</b> transistors; but it's not going in a laptop anytime soon, it uses 15 KW of power.</span></span><o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><span style='font-size:13.5pt'><a href="https://www.tomshardware.com/news/worlds-biggest-chip-cerebras-7nm-26-trillion-transistors-850000-cores-wafer-scale-engine" target="_blank">World's Largest Chip with 2.6 Trillion 7nm Transistors and 850,000 Cores</a></span><o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><span style='font-size:13.5pt;font-family:"Arial",sans-serif'>John K Clark</span><span style='font-family:"Arial",sans-serif'><o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>>…But how many millimeters across is it? What is its surface area and volume? If it is to be the "largest" chip, these dimensions should be provided.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>They do: 46k mm^2. That dude would be about the size of a salad plate.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Cool! It would need to be that size to be cool.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I don’t know how it is done in the new days, but in the olden days, all the calculation was done at the core, then all the I/O stuff had to be serially amplified up to the periphery to interface with 5 vdc and the giant meat beasts who supply the power, out in the great unknown, from unfathomable distances, hundreds of meters away.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>Most of the power of a chip back then was in I/O.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>I was wondering if there was a way to do massively parallel operations with a bunch of cores handing results to each other and not ramping the signal back up to our scale until the endgame.<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal>spike<o:p></o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p><p class=MsoNormal><o:p> </o:p></p></div></div></body></html>