[extropy-chat] diffraction limit

[Dan Clemmensen]

scerir wrote:

>Anyway, let me point out this paper (it seems a very good one)
>http://www.intel.com/research/documents/Bourianoff-Proc-IEEE-Limits.pdf
> 
>  
>
Thanks! Very interesting paper. Assuming I understand it correctly, it 
says that no matter how you build it or what you build it out  of, 
digital electronics cannot be packed more closely that about 20 nm 
cubed. Each such cube can contain a piece of interconnect, a gate, or a 
flip-flop. And yes, I'm making a very free interpretation of the paper.

The paper is almost entirely about 2D systems. For a 2D system, with 
flip-flops of 20nm squared, the heat dissipation will be about 60W/cm 
squared.

To a first approximation, this paper concludes that the practical limits 
of electronic computation coincide with the practical limits of CMOS, 
and are consistent with the Moore's-law industry roadmap's goal for the 
year 2017.

Note that these limits will are for CPUs (i.e, each cell changes state 
frequently) as opposed to memory. A nanomechanical memory can be as much 
as 1000 times denser than a nano-electronic CPU.