[ExI] how would Transhumanists cope if the Singularity did not happen in their lifetime?

[Eugen Leitl]

On Tue, May 15, 2007 at 01:30:37PM +0100, Russell Wallace wrote:

>      No, it isn't. Read the original paper.
> 
>    I'm well aware of what the original paper said. My point stands: if

Then you're claiming more than Moore even did.

>    increased integration density didn't result in increased performance,
>    nobody would bother referring to that paper, let alone enshrining said
>    reference in the vernacular.

The claim is not just in increased performance, but specifically, in
a linear semi-log plot increased performance. That claim is
bogus, and repetitions do not make it any more true.
(No, the aggregated TOP 500 is not about Moore, so you don't
have to cite that).
 
>      Computer performance, as measured in benchmarks, does not result
>      in linear semi-log plot.
> 
>    Yes it does.

Benchmarks proving your point, please.
 
>      Case in point: the difference between CPU speed, as measured
>      by benchmarks, and memory bandwidth, as measured by benchmarks,
>      is a linear semi-log plot.
>      But you knew that already.
> 
>    Well yes. And each of the components are (approximately) linear
>    semi-log. As is RAM capacity. As is disk capacity. As is the bandwidth

So is memory bandwidth versus time a linear semi-log, yes or no?

>    of a fixed amount of memory (as it migrates from disk to RAM to cache
>    - a steeper semi-log than the bandwidth of main memory). Stepping

Moore is not about hard drive storage, and incidentally, the
hard drive latency is *also* not a linear semi-log plot. Same applies
to tape.

>    back, we see it's actually a pyramid, with disk at the base and
>    registers at the peak; the height of the peak (speed of operation on

I'm very faimiliar with computer architecture 101, thanks. Since
actual code doesn't run out of registers only, nonsynthentic benchmarks
support my point, and not yours.

>    registers), the width of the base (disk capacity) and the width of the
>    second layer (RAM) are all best approximated as linear semi-log.

You're starting to sound like Kurzweil. If reality doesn't fit your
requirements, you design a synthetic benchmark of no relevance to
reality.

I'm sorry, a waferful of ring oscillators might fit Moore quite closely,
but 

0) it's not something you can buy 
beta) it won't make your benchmarked code fit semilinear log plot
      with each semiconductor lithography node

So, if you have to add to your claims, I'm willing to listen to
*real-world* benchmarks (no, Linpack is not a real-world benchmark)
confirming your point. 

Unless you can back your claim up with that, spare your keystrokes.

-- 
Eugen* Leitl <a href="http://leitl.org">leitl</a> http://leitl.org
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