[ExI] moar Moore

Kelly Anderson kellycoinguy at gmail.com
Thu Oct 31 18:37:40 UTC 2013

On Wed, Oct 30, 2013 at 10:37 AM, Eugen Leitl <eugen at leitl.org> wrote:

> The sheer density and power levels on a state-of-the-art chip have forced
> designers to compensate by adding error-correction circuitry, redundancy,
> read- and write-boosting circuitry for failing static RAM cells, circuits
> to
> track and adapt to performance variations, and complicated memory
> hierarchies
> to handle multicore architectures. The problem, Kahng says, is that “all of
> those extra circuits add area.” His group has been scouring company specs
> and
> deconstructing images of chips for years, and they’ve come to an unsettling
> conclusion: When you factor those circuits in, chips are no longer twice as
> dense from generation to generation. In fact, Kahng’s analysis suggests,
> the
> density improvement over the past three generations, from 2007 on, has been
> closer to 1.6 than 2. This smaller density benefit means costlier chips,
> and
> it also has an impact on performance because signals must be driven over
> longer distances. The shortfall is consistent enough, Kahng says, that it
> could be considered its own law.

To me, this was the most concerning paragraph in this article. If you have
to add more error correcting logic to make increasingly unreliable small
components perform in a reliable fashion, then you aren't getting
performance increases.

> When will the scaling stop? Today’s patterning technology, which relies on
> 193-nm laser light, is becoming an ever more costly challenge, and its
> natural successor, shorter-wavelength extreme ultraviolet lithography, has
> been long delayed.

Sounds like an interesting direction to go.

> Many people in the industry, who have watched showstopper after showstopper
> crop up only to be bypassed by a new development, are reluctant to put a
> hard
> date on Moore’s Law’s demise. “Every generation, there are people who will
> say we’re coming to the end of the shrink,”

One named Eugen... :-)

> says ASML’s Arnold, and in “every
> generation various improvements do come about. I haven’t seen the end of
> the
> road map.”

And there you have it. Improvement, but perhaps not at the same breakneck

I wonder if they will start building ICs on something like cardboard
waferboard. That is, all crinkled up... That would be another way to get
towards 2.5 D configurations, particularly if you put two sheets of them
together face to face...

I'm not sure, but I am hopeful that we will see increased performance,
combined with decreased pricing for many years to come. If not, it will
signal the end of this particular brand of exponential improvement.

I was also concerned about marketing taking over naming conventions.
Although, if you have more transistors per sq cm, is that not good enough?
And are they getting that? The article didn't say.

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